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rev. 1.20 1 may 10, 2011 HT16C22/HT16C22g ram mapping 44*4 lcd controller driver features operating voltage:2.4~5.5v internal 32khz rc oscillator bias: 1/2 or 1/3; duty: 1/4 internal lcd bias generation with voltage-follower buffers i 2 c-bus interface two selectable lcd frame frequencies: 80hz or 160hz 44 x 4 bits ram for display data storage max. 44 x 4 patterns, 44 segments and 4 commons versatile blinking modes r/w address auto increment internal 16-step voltage adjustment to adjust lcd operating voltage low power consumption provides v lcd pin to adjust lcd operating voltage manufactured in silicon gate cmos process package type: 48lqfp, 52qfp, chip and cog. general description the HT16C22/HT16C22g device is a memory mapping and multi-function lcd controller driver. the maximum display segments of the device are 176 patterns (44 segments and 4commons). the software con guration feature of the HT16C22/HT16C22g makes it suitable for multiple lcd applications including lcd modules and display subsystems. the HT16C22/HT16C22g device communicates with most microprocessors / microcontrollers via a two-line bidirectional i 2 c-bus. applications electronic meter water meter gas meter heat energy meter household appliance games telephone consumer electronics
rev. 1.20 2 may 10, 2011 HT16C22/HT16C22g block diagram lcd voltage selector column driver output segment driver output display ram 44*4its timing generator i2c controller com0 com3 seg0 vlcd vss sda scl internal rc oscillator power_on reset r op1 seg43 vdd lcd bias generator r 8 r op2 internal voltage adjustment op3
rev. 1.20 3 may 10, 2011 HT16C22/HT16C22g pin assignment

note: the *com1 and *com2 pins are not in sequential order. note: the *com1 and *com2 pins are not in sequential order.
rev. 1.20 4 may 10, 2011 HT16C22/HT16C22g pad assignment for cob

chip size: 1673 x 1676 um 2 note: 1. the option0 (pad7) should be bonded to v dd or oating. 2. the option1 (pad2) should be bonded to v ss or oating. 3. the ic substrate should be connected to v ss in the pcb layout artwork 4. the *com1 and *com2 pins are not in sequential order. internal voltage adjustment (iva) set command vlcd (pad1) segment43 (pad56) note de bit ve bit 0 0 input null the vlcd input voltage can be smaller than or equal to vdd 0 1 output null the vlcd pin is an output pin of which the voltage can be detected by the external mcu host. 1 0 null output ? 1 1 null output ?
rev. 1.20 5 may 10, 2011 HT16C22/HT16C22g pad coordinates for cob unit: m no pad name x y no pad name x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vlcd option1 vdd sda scl vss option0 com0 *com2 *com1 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 n.c. seg12 seg13 seg14 seg15 -695.6 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -732.9 -409.85 -324.85 -239.85 -154.85 -69.85 15.15 100.15 185.15 70.747 270.15 355.15 440.15 525.15 734.4 421.349 336.349 251.349 166.349 81.349 -3.801 -102.1 -187.1 -272.1 -357.1 -442.1 -527.1 -612.1 -697.1 -734.4 -734.4 -734.4 -734.4 -734.4 -734.4 -734.4 -734.4 -239.021 -734.4 -734.4 -734.4 -734.4 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 610.15 695.15 732.45 732.45 732.45 732.45 732.45 732.45 732.45 732.45 732.45 732.45 732.45 732.45 732.45 409.4 324.4 239.4 154.4 69.4 -15.6 -100.6 -185.6 -270.6 -355.6 -440.6 -525.6 -610.6 -734.4 -734.4 -411.35 -326.35 -241.35 -156.35 -71.35 13.65 98.65 183.65 268.65 353.65 527.1 612.1 697.1 734.4 734.4 734.4 734.4 734.4 734.4 734.4 734.4 734.4 734.4 734.4 734.4 734.4 note: the *com1 and *com2 pins are not in sequential order.
rev. 1.20 6 may 10, 2011 HT16C22/HT16C22g pad assignment for cog (0, 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 73 7271 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 note: internal voltage adjustment (iva) set command vlcd (pad14) segment43 (pad5) note de bit ve bit 0 0 input null the vlcd input voltage can be smaller than or equal to vdd 0 1 output null the vlcd pin is an output pin of which the voltage can be detected by the external mcu host. 1 0 null output ? 1 1 null output ? pad dimensions for cog item number. size unit xy chip size ? 2666 948 m chip thickness ? 508 m pad pitch 1~7, 27~73 60 m 9~25 87 m bump size output pad 34~73 40 60 m 2~5, 29~32 60 40 m input pad 10~14 67 67 m dummy pad 1, 33 40 60 m 6~7, 27~28 60 40 m 9, 15~25 67 67 m bump height all pad 183 m
rev. 1.20 7 may 10, 2011 HT16C22/HT16C22g alignment mark dimensions for cog item number size unit align_a 8 40um 20um 20um (-1237.5, 285) 10um 10um 10um 10um m align_b 26 20um 20um 20um 20um (1237.5, -285) 10um 10um 10um 10um m
rev. 1.20 8 may 10, 2011 HT16C22/HT16C22g pad coordinates for cog unit: m no name x y no name x y 1 dummy -1230 379.5 39 seg5 870 379.5 2 seg40 -1238.5 86.25 40 seg6 810 379.5 3 seg41 -1238.5 26.25 41 seg7 750 379.5 4 seg42 -1238.5 -33.75 42 seg8 690 379.5 5 seg43 -1238.5 -93.75 43 seg9 630 379.5 6 dummy -1238.5 -153.75 44 seg10 570 379.5 7 dummy -1238.5 -213.75 45 seg11 510 379.5 9 dummy -1235 -370.4 46 seg12 450 379.5 10 sda -933 -370.4 47 seg13 390 379.5 11 scl -846 -370.4 48 seg14 330 379.5 12 vdd -575 -370.4 49 seg15 270 379.5 13 vss -488 -370.4 50 seg16 210 379.5 14 vlcd -300 -370.4 51 seg17 150 379.5 15 dummy 365 -370.4 52 seg18 90 379.5 16 dummy 452 -370.4 53 seg19 30 379.5 17 dummy 539 -370.4 54 seg20 -30 379.5 18 dummy 626 -370.4 55 seg21 -90 379.5 19 dummy 713 -370.4 56 seg22 -150 379.5 20 dummy 800 -370.4 57 seg23 -210 379.5 21 dummy 887 -370.4 58 seg24 -270 379.5 22 dummy 974 -370.4 59 seg25 -330 379.5 23 dummy 1061 -370.4 60 seg26 -390 379.5 24 dummy 1148 -370.4 61 seg27 -450 379.5 25 dummy 1235 -370.4 62 seg28 -510 379.5 27 dummy 1238.5 -213.75 63 seg29 -570 379.5 28 dummy 1238.5 -153.75 64 seg30 -630 379.5 29 com0 1238.5 -93.75 65 seg31 -690 379.5 30 com1 1238.5 -33.75 66 seg32 -750 379.5 31 com2 1238.5 26.25 67 seg33 -810 379.5 32 com3 1238.5 86.25 68 seg34 -870 379.5 33 dummy 1230 379.5 69 seg35 -930 379.5 34 seg0 1170 379.5 70 seg36 -990 379.5 35 seg1 1110 379.5 71 seg37 -1050 379.5 36 seg2 1050 379.5 72 seg38 -1110 379.5 37 seg3 990 379.5 73 seg39 -1170 379.5 38 seg4 930 379.5 alignment mark coordinates for cog no name x y no name x y 8 align_a -1237.5 -285 26 align_b 1237.5 -285
rev. 1.20 9 may 10, 2011 HT16C22/HT16C22g pin description pin name type description sda i/o serial data input/output for i 2 c interface scl i serial clock input for i 2 c vdd D positive power supply. vss D negative power supply , ground. vlcd D one external resistor is connected between the vlcd pin and the vdd pin to determine the bias voltage for package with a vlcd pin. internal voltage adjustment function is disabled. internal voltage adjustment function can be used to adjust the vlcd voltage. if the vlcd pin is used as voltage detection pin, an external power supply should not be applied to the vlcd pin. an external mcu can detect the voltage of the vlcd pin and program the internal voltage adjustment for packages with a vlcd pin. com0~com3 o lcd common outputs. seg0~seg43 o lcd segment outputs. approximate internal connections v ss ? 0.3v to v ss +6.5v v ss ? 0.3v to v dd +0.3v ? 55c to 150c ? 40c to 85c absolute maximum ratings supply voltage input voltage storage temperature operating temperature these are stress ratings only. stresses exceeding the range speci ed under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. note : ! " # " $ % & ' ( ! " # " $ % & ' ) ) * *
rev. 1.20 10 may 10, 2011 HT16C22/HT16C22g d.c. characteristics v ss = 0 v; v dd = 2.4 to 5.5 v; t a = ? 40 to +85 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage DD 2.4 D 5.5 v v lcd operating voltage DD DD v dd v i dd operating current 3v no load, v lcd =v dd , 1/3bias f lcd =80hz, lcd display on, internal system oscillator on,. da0~da3 are set to "0000" D 18 27 a 5v D 25 40 a i dd1 operating current 3v no load, v lcd =v dd , 1/3bias f lcd =80hz, lcd display off, internal system oscillator on, da0~da3 are set to "0000" D 25 a 5v D 410 a i stb standby current 3v no load, v lcd =v dd , lcd display off, internal system oscillator off, DD 1 a 5v DD 2 a v ih input low voltage D sda , scl 0.7v dd D v dd v v il input low voltage for sda and scl pins DD 0 D 0.3v dd v i il input leakage current D v in = v ss or v dd -1 D 1 a i ol low level output current 3v v ol =0.4v on sda pin 3 DD ma 5v 6 DD ma i ol1 lcd common sink current 3v v lcd =3v, v ol =0.3v 250 400 D a 5v v lcd =5v, v ol =0.5v 500 800 D a i oh1 lcd common source current 3v v lcd =3v, v oh =2.7v -140 -230 D a 5v v lcd =5v, v oh =4.5v -300 -500 D a i ol2 lcd segment sink current 3v v lcd =3v, v ol =0.3v 250 400 D a 5v v lcd =5v, v ol =0.5v 500 800 D a i oh2 lcd segment source current 3v v lcd =3v, v oh =2.7v -140 -230 D a 5v v lcd =5v, v oh =4.5v -300 -500 D a a.c. characteristics v ss = 0 v; v dd = 2.4 to 5.5 v; t a = ? 40 to +85 c symbol parameter test conditions min. typ. max. unit v dd conditions f lcd1 lcd frame frequency 4v 1/4 duty, t a =25 c 72 80 88 hz f lcd2 lcd frame frequency 4v 1/4 duty, t a = ? 40 to +85 c 52 80 124 hz f lcd3 lcd frame frequency 4v 1/4 duty, t a =25 c 144 160 176 hz f lcd4 lcd frame frequency 4v 1/4 duty, t a = ? 40 to +85 c 104 160 248 hz t off v dd off times D v dd drop down to 0v 20 DD ms t sr v dd slew rate DD 0.05 DD v/ms if the power on reset timing conditions are not satis ed during the power on/off sequence, the internal power on reset circuit will not operate normally. if v dd drops below the minimum voltage of operating voltage spec. during operating, the power on reset timing conditions must also be satis ed. that is, v dd must drop to 0v and remain at 0v for 20ms (min.) before rising to its normal operating voltage. note :
rev. 1.20 11 may 10, 2011 HT16C22/HT16C22g a.c. characteristics - i 2 c interface symbol parameter conditions v dd =2.4v to 5.5v v dd =3.0v to 5.5v unit min. max. min. max. f scl clock frequency DD 100 D 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 4.7 D 1.3 D s t hd;sta start condition hold time after this period, the rst clock pulse is generated 4 D 0.6 D s t low scl low time D 4.7 D 1.3 D s t high scl high time D 4 D 0.6 D s t su;sta start condition setup time only relevant for repeated start condition. 4.7 D 0.6 D s t hd;dat data hold time D 0 D 0 D ns t su;dat data setup time D 250 D 100 D ns t r sda and scl rise time note* D 1 D 0.3 s t f sda and scl fall time note* D 0.3 D 0.3 s t su;sto stop condition set-up time D 4 D 0.6 D s t aa output valid from clock DD 3.5 D 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time D 100 D 50 ns these parameters are periodically sampled but not 100% tested. note : timing diagrams i 2 c timing power on reset timing the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the valid start condition of a sequential command. note :
rev. 1.20 12 may 10, 2011 HT16C22/HT16C22g functional description power-on reset when power is applied, the device is initialised by an internal power-on reset circuit. the status of the internal circuits after initialisation is as follows: all common outputs are set to v dd all segment outputs are set to v dd the drive mode 1/4 duty output and 1/3 bias is selected the system oscillator and the lcd bias generator is off state lcd display is off state internal voltage adjustment function is enabled detection switch for v lcd pin is disabled frame frequency is set to 80hz blinking function is switched off data transfers on the i 2 c-bus should be avoided for 1 ms following power-on to allow completion of the reset action. display memory - ram structure the display ram is a static 44 x 4-bit ram which stores lcd data. logic ?1? in the ram bit-map indicates the ?on? state of the corresponding lcd segment; similarly logic 0 indicates the ?off? state. the contents of the ram data are directly mapped to the lcd data. the first ram column corresponds to the 44 segments operated with respect to com0. in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with com1, com2 and com3 respectively. the following is a mapping from the ram data to the lcd pattern: output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 0 seg3 seg2 1 seg5 seg4 2 seg7 seg6 3 seg9 seg8 4 seg11 seg10 5 seg43 seg42 21 d7 d6 d5 d4 d3 d2 d1 d0 data display data transfer format for the i 2 c bus system oscillator the timing for the internal logic and the lcd drive signals are generated by an internal oscillator. the system clock frequency (f sys ) determines the lcd frame frequency. during initial system power on the system oscillator will be in the stop state. d0 msb lsb d1 d2 d3 d4 d5 d6 d7
rev. 1.20 13 may 10, 2011 HT16C22/HT16C22g seg n+2 seg n+2 v lcd v lcd v ss v ss seg n seg n com0 com0 com1 com1 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd com2 com2 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 lcd bias generator the full-scale lcd voltage (v op ) is obtained from v lcd ? v ss . the lcd voltage may be temperature compensated externally through the voltage supply to the vlcd pin. fractional lcd biasing voltages are obtained from an internal voltage divider of three series resistors connected between v lcd and v ss . the centre resistor can be switched out of the circuits to provide a 1/2 bias voltage level for the 1/4 duty con guration. lcd drive mode waveforms when two columns are provided in the lcd, the 1/4duty drive mode applies. the HT16C22/HT16C22g can use 1/2 or 1/3 bias types in output waveforms as shown as follows: waveforms for 1/4 duty drive mode with1/2 bias (v op =v lcd -v ss )
rev. 1.20 14 may 10, 2011 HT16C22/HT16C22g seg n+2 seg n+2 seg n seg n com0 com0 com1 com1 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd com2 com2 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 waveforms for 1/4 duty drive mode with1/3 bias (v op =v lcd -v ss )
rev. 1.20 15 may 10, 2011 HT16C22/HT16C22g segment driver outputs the lcd drive section includes 44 segment outputs seg0 to seg43 which should be connected directly to the lcd panel. the segment output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. when less than 44 segment outputs are required the unused segment outputs should be left open-circuit. column driver outputs the lcd drive section includes four column outputs com0 to com3 which should be connected directly to the lcd panel. the column output signals are generated in accordance with the selected lcd drive mode. when less than 4 column outputs are required the unused column outputs should be left open-circuit. address pointer the addressing mechanism for the display ram is implemented using the address pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialisation of the address pointer by the address pointer command. blinker function the device contains versatile blinking capabilities. the whole display can be blinked at frequency selected by the blink command. the blinking frequency is a subdivided ratio of the system frequency. the ratio between the system oscillator and blinking frequency depends on the blinking mode in which the device is operating in, as shown in the table: blinking mode operating mode ratio blinking frequency (hz) 0 0 blink off 1f sys / 16384hz 2 2f sys / 32768hz 1 3f sys / 65536hz 0.5 frame frequency the HT16C22/HT16C22g provides two frame frequencies selected with the mode set command; 80hz and 160hz. v lcd voltage adjustment the internal v lcd adjustment contains four resistors in series and a 4- bit programmable analog switch which can provide sixteen voltage adjustment options using the vlcd voltage adjustment command. the v lcd adjustment structure is show in the diagram: r r r 16r/15 8r/15 4r/15 2r/15 da3 da2 da1 da0 internal voltage adjustment lcd bias generator v dd v lcd pin
rev. 1.20 16 may 10, 2011 HT16C22/HT16C22g the relationship between the programmable 4-bit analog switch and the v lcd output voltage is shown in the table: 1/2 1/3 note 00h 1.000*v dd 1.000*v dd default value 01h 0.9375*v dd 0.957*v dd ? 02h 0.882*v dd 0.918*v dd ? 03h 0.833*v dd 0.882*v dd ? 04h 0.789*v dd 0.849*v dd ? 05h 0.750*v dd 0.818*v dd ? 06h 0.714*v dd 0.789*v dd ? 07h 0.682*v dd 0.763*v dd ? 08h 0.652*v dd 0.738*v dd ? 09h 0.625*v dd 0.714*v dd ? 0ah 0.600*v dd 0.692*v dd ? 0bh 0.577*v dd 0.672*v dd ? 0ch 0.556*v dd 0.652*v dd ? 0dh 0.536*v dd 0.634*v dd ? 0eh 0.517*v dd 0.616*v dd ? 0fh 0.500*v dd 0.600*v dd ? da3~da0 bias i 2 c serial interface the device includes an i 2 c serial interface. the i 2 c bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line, sda, and a serial clock line, scl. both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7k . when the bus is free, both lines are high. devices connected to the bus must have open-drain or open-collector outputs to implement a wired-or function. data transfer is initiated only when the bus is not busy. data validity the data on the sda line must be stable during the high period of the serial clock. the high or low state of the data line can only change when the clock signal on the scl line is low as shown in the diagram. start and stop conditions a high to low transition on the sda line while scl is high de nes a start condition a low to high transition on the sda line while scl is high de nes a stop condition start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in some respects, the start(s) and repeated start (sr) conditions are functionally identical. p s sda scl sda scl start condition stop condition sda scl data line stable, data valid chang of data allowed
rev. 1.20 17 may 10, 2011 HT16C22/HT16C22g byte format every byte placed on the sda line must be 8-bits in length. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most signi cant bit, msb, rst. acknowledge each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a low level placed on the bus by the receiver. the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge bit, ack, after the reception of each byte. the device that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse a master receiver must signal an end of data to the slave by generating a not-acknowledge, nack, bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. the master will generate a stop or repeated start condition. slave addressing the slave address byte is the rst byte received following the start condition form the master device. the rst seven bits of the rst byte make up the slave address. the eighth bit de nes a read or write operation to be performed. when the r/w bit is ?1?, a read operation is selected. a ?0? selects a write operation. the HT16C22/HT16C22g address bits are ?0 11111 1?. when an address byte is sent, the device compares the rst seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. s or sr p or sr sda scl 12 78 9 ack 12 3-8 9 ack p sr s 12 78 9 clk pulse for acknowledgement data output by transmiter data output by receiver scl from master acknowledge not acknowledge start condition r/w 1 1 1 1 1 1 1 0 msb lsb
rev. 1.20 18 may 10, 2011 HT16C22/HT16C22g byte write operation a byte write operation requires a start condition, a slave address with an r/w bit, a valid register address, data and a stop condition. after each of the three bytes, the device responds with an ack. command byte received single data byte received page write operation after a start condition the slave address with the r/w bit is placed on the bus followed with the register address of which the contents are written to the internal address pointer. the data to be written to the memory will be transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock. after the internal address point reaches the maximum memory address, which is 15h, the address pointer will be reset to 00h. byte write operation if the byte following the slave address is a command code, the byte following the command code will be ignored. note : n data bytes received in this mode, the master reads the HT16C22/HT16C22g data after setting the slave address. following the r/w bit (=?0?) is an acknowledge bit and the register address (an) which is written to the internal address pointer. after the start address of the read operation has been con gured, another start condition and the slave address are transferred on the bus followed by the r/w bit (=?1?). then the msb of the data which was addressed is transmitted rst on the i2c bus. the address pointer is only incremented by 1 after the reception of an acknowledge clock. that means that if the device is con gured to transmit the data at the address of an+1, the master will read and acknowledge the transferred new data byte and the internal address pointer is incremented to an+2. after the internal address pointer reaches the maximum memory address which is 15h, the pointer will be reset to 00h. this cycle of reading consecutive addresses will continue until the master sends a stop condition. read operation slave address ack write command byte ack p s01111110 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 slave address ack write command / register address byte ack s01111110 data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
rev. 1.20 19 may 10, 2011 HT16C22/HT16C22g ack write command / register address byte ack p slave address s01111110 data byte nack d7 d6 d5 d4 d3 d2 d1 d0 1st data data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 nth data data byte d7 d6 d5 d4 d3 d2 d1 d0 2nd data ack ack device address read s01111111 ack bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reading n data bytes
rev. 1.20 20 may 10, 2011 HT16C22/HT16C22g command summary lcd driver mode set: these commands set the frame frequency output and internal system oscillator on/off and display on/off and driver mode set. msb lsb function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note def mode set 1 0 0 f s e 0 m0 80h note: 1. when ?m0? is set to ?0?: the driver mode is set to 1/3bias. 2. when ?m0? is set to ?1?: the driver mode is set to 1/2bias. 3. when ?s? and ?e? bits are set to {0, x}: display off and disable internal system oscillator. 4. when ?s? and ?e? bits are set to {1, 0}: display off and enable internal system oscillator. 5. when ?s? and ?e? bits are set to {1, 1}: display on and enable internal system oscillator. 6. when ?f? bits is set to ?0?: frame frequency=80hz 7. when ?f? bits is set to ?1?: frame frequency=160hz 8. power on status: the drive mode 1/3 bias is selected display off and disable internal system oscillator frame frequency is set to 80hz 9. if programmed command data is not de ned, the function will not be affected. display data input setting: this command sends data from mcu to memory map of HT16C22/HT16C22g. msb lsb function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note def address pointer 0 0 0 a4 a3 a2 a1 a0 display data start address of memory map 00h note: 1. power on status: the address is set to 00h. 2. after reaching the memory location 15h, the pointer will reset to 00h. 3. if programmed command data is not de ned, the function will not be affected.
rev. 1.20 21 may 10, 2011 HT16C22/HT16C22g blinking setting command: these commands set the blinking frequency of display modes. msb lsb function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note def blinking frequency 110000bk1bk0 c0h note: 1. when ?bk1? and ?bk0? bits are set to {0, 0}: blinking off 2. when ?bk1? and ?bk0? bits are set to {0, 1}: blinking frequency= 2hz 3. when ?bk1? and ?bk0? bits are set to {1, 0}: blinking frequency= 1hz 4. when ?bk1? and ?bk0? bits are set to {1, 1}: blinking frequency= 0.5hz 5. power on status: blinking is switched off. 6. if programmed command data is not de ned, the function will not be affected.
rev. 1.20 22 may 10, 2011 HT16C22/HT16C22g internal voltage adjustment (iva) setting command: the internal voltage (v lcd ) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting lcd operating voltage adjustment command code. msb lsb function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note def internal voltage adjust control 0 1 de ve da3 da2 da1 da0 the segment/ vlcd shared pin can be programmed via the ?de? bit the ?ve? bit is used to enable or disable the internal voltage adjustment for bias voltage. da3~da0 can be used to adjust the v lcd output voltage. 70h note: 1. when ?de? and ?ve? bits are set to {0, 0}: the segment/ vlcd shared pin is set as vlcd pin. disable internal voltage adjustment. one external resister must be connected between vlcd pin and vdd pin to determine the bias voltage, and internal voltage follower (op3) must be enabled by setting da3~da0 as the value other than ?0000?. if vlcd pin is connected to vdd pin, the internal voltage follower (op3) must be disabled by setting da3~da0 as ?0000?. 2. when ?de? and ?ve? bits are set to {0,1}: the segment/ vlcd shared pin is set as vlcd pin. enable internal voltage adjustment. the external mcu can detect the voltage of vlcd pin. 3. when ?de? and ?ve? bits are set to {1,0}: the segment/ vlcd shared pin is set as segment pin. disable internal voltage adjustment. the bias voltage is supplied by internal vdd power. the internal voltage-follower (op3) is disabled automatically when de & ve is set as ?10?. da3~da0 don?t care. 4. when ?de? and ?ve? bits are set to {1,1}: the segment/ vlcd shared pin is set as segment pin. enable internal voltage adjustment. 5. when da0~da3 bits are set to ?0000?, internal voltage-follower (op3) is disabled. when da0~da3 bits are set to other values, internal voltage follower (op3) is enabled. 6. power output status: enable internal voltage adjustment and segment/vlcd pin is set as the segment pin. 7. if programmed command data is not de ned, the function will not be affected.
rev. 1.20 23 may 10, 2011 HT16C22/HT16C22g HT16C22/HT16C22g operation flow chart access procedures are illustrated below by means of owcharts. initialization power on segment / vlcd shared pin setting internal lcd frame frequency setting internal lcd bias setting lcd blinking frequency setting next processing
rev. 1.20 24 may 10, 2011 HT16C22/HT16C22g display data read/write(address setting) start next processing display data ram write address setting display on and enable internal system clock
rev. 1.20 25 may 10, 2011 HT16C22/HT16C22g segment / vlcd share pin setting and internal voltage adjustment setting. segment / vlcd share pin setting the bias voltage is supplied by programmable internal voltage adjustment one external resistor must be connected between to vlcd pin and vdd pin to determine the bias voltage internal voltage adjustment enable ? the external mcu can detect the voltage of vlcd pin. yes no start set as segment pin. the bias voltage is supplied by internal vdd power. next processing set as vlcd pin. internal voltage adjustment enable ? no yes
rev. 1.20 26 may 10, 2011 HT16C22/HT16C22g application circuit set as segment pin 1. disable internal voltage adjustment 2. the bias voltage is supplied by internal vdd power. 3. enable internal voltage 4. the internal voltage adjustment for bias voltage lcd panel com0~com3 seg0~segx com0~com3 seg0~segx scl sda vdd vss mcu vdd vss HT16C22 vdd vss 0.1uf 4.7k 4.7k lcd panel com0~com3 seg0~segx com0~com3 seg0~segx scl sda vdd vss mcu vdd vss HT16C22 vdd vss 0.1uf 4.7k 4.7k
rev. 1.20 27 may 10, 2011 HT16C22/HT16C22g set as vlcd pin 1. disable internal voltage adjustment 2. one external resister must be connected between vlcd pin and vdd pin to determine the bias voltage 3. enable internal voltage adjustment 4. the external mcu can detect the voltage of vlcd pin. vr lcd panel com0~com3 seg0~segx com0~com3 seg0~segx scl sda vdd vss mcu vdd vss HT16C22 vdd vss 0.1uf vlcd 4.7k 4.7k lcd panel com0~com3 seg0~segx com0~com3 seg0~segx scl sda vdd vss vdd vss HT16C22 vdd vss 4.7k 0.1uf vlcd mcu 4.7k
rev. 1.20 28 may 10, 2011 HT16C22/HT16C22g package information
symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.020 D f D 0.008 D g 0.053 D 0.057 h DD 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.20 D g 1.35 D 1.45 h DD 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7 48-pin lqfp (7mmx7mm) outline dimensions
rev. 1.20 29 may 10, 2011 HT16C22/HT16C22g symbol dimensions in inch min. nom. max. a 0.681 D 0.689 b 0.547 D 0.555 c 0.681 D 0.689 d 0.547 D 0.555 e D 0.039 D f D 0.016 D g 0.098 D 0.122 h DD 0.134 i D 0.004 D j 0.029 D 0.041 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 17.30 D 17.50 b 13.90 D 14.10 c 17.30 D 17.50 d 13.90 D 14.10 e D 1.00 D f D 0.40 D g 2.50 D 3.10 h DD 3.40 i D 0.10 D j 0.73 D 1.03 k 0.10 D 0.20 0 D 7
52-pin qfp (14mmx14mm) outline dimensions
rev. 1.20 30 may 10, 2011 HT16C22/HT16C22g holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales of ce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales of ce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales of ce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modi cation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior noti cation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw .

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